554AF000141DG【PDF 1/15 页】OSCILLATOR VCXO 8-PIN

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Sheet目录653

[1页]2页 3页 4页 5页

Si 5 54

R EVISION D

Q UAD F R E Q U E N C Y V O L TAG E - C O N T R O L L E D C RYSTAL

O SCILLATOR ( V C X O ) 1 0 MH Z TO 1.4 G H Z

Features

Available with any-rate output

frequencies from 10–945 MHz and

selected frequencies to 1.4 GHz

Four selectable output frequencies

3rd generation DSPLL ? with superior

jitter performance

3x better frequency stability than

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

Si5602

SAW-based oscillators

Applications

package and pinout

Pb-free/RoHS-compliant

Ordering Information:

SONET/SDH

xDSL

10 GbE LAN / WAN

Low jitter clock generation

Optical modules

Clock and data recovery

See page 10.

Pin Assignments:

Description

The Si554 quad-frequency VCXO utilizes Silicon Laboratories’ advanced

DSPLL ? circuitry to provide a very low jitter clock for all output frequencies.

The Si554 is available with any-rate output frequency from 10 to 945 MHz

See page 9.

(Top View)

FS[1]

and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a

different crystal is required for each output frequency, the Si554 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

V C

V DD

IC-based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

CLK–

provides superior supply noise rejection, simplifying the task of generating

low jitter clocks in noisy environments typically found in communication

systems. The Si554 IC-based VCXO is factory-configurable for a wide

variety of user specifications including frequency, supply voltage, output

GND

CLK+

format, tuning slope, and temperature stability. Specific configurations are

factory-programmed at time of shipment, thereby eliminating the long lead

times associated with custom oscillators.

Functional Block Diagram

FS[0]

V DD

Any-rate

CLK- CLK+

FS1

Fixed

Frequency XO

10–1400 MHz

DSPLL ?

FS0

Clock Synthesis

ADC

V c

GND

Rev. 1.1 4/13

Si554

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